1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and more particularly, to a structure of a memory cell in a nonvolatile random access memory device which can be also used as a dynamic random access memory and an electrically programmable and erasable memory.
2. Description of the Prior Art
An electrically programmable nonvolatile semiconductor memory device includes an EEPROM (electrically erasable and programmable read only memory). The EEPROM has some disadvantages. For example, it requires a data writing time on the order of the millisecond and has a limitation to the number of times of rewriting data. Therefore, a conventional nonvolatile random access memory device (referred to as a nonvolatile RAM hereinafter) is achieved by a combination of a static RAM memory cell in which data can be read and written at the high speed and an EEPROM memory cell in which information can be stored in a nonvolatile manner.
FIG. 1 is a diagram showing an example of a structure of a memory cell in a conventional nonvolatile RAM, which is disclosed in, for example, ISSCC Digest of Technical Papers, February 1983, page 170. In FIG. 1, the memory cell in the conventional nonvolatile RAM comprises a static RAM memory cell portion 1 and an EEPROM memory cell portion 2.
The static RAM cell portion 1 comprises a flip-flop including n channel MOS transistors Q1 to Q4 and transfer gates Q5 and Q6 for transferring data from the flip-flop to a pair of bit lines BL and BL or vise versa.
The flip-flop comprises the n channel MOS transistors Q1 and Q2 each having a gate and a drain cross-connected to each other, the transistor Q3 of a depletion type having one conduction terminal connected to a power supply V.sub.DD and a gate and other conduction terminal each connected to the gate of the MOS transistor Q2, and the MOS transistor Q4 of a depletion type having one conduction terminal connected to the power supply V.sub.DD and a gate and other conduction terminal each connected to the gate of the MOS transistor Q1. The transfer gate Q5 has one conduction terminal connected to the bit line BL, other conduction terminal connected to a node of the MOS transistors Q1 and Q3 and a gate connected to a word line WL. The transfer gate Q6 has one conduction terminal connected to the bit line BL, other conduction terminal connected to a node of the MOS transistors Q2 and Q4 and a gate connected to the word line WL.
The EEPROM memory cell portion 2 comprises a transfer gate Q8 for transferring data from/to the static RAM cell portion 1, a transistor Q7 of an FLOTOX (floating gate tunnel oxide film) type for storing information in a nonvolatile manner, and a transistor Q9 serving as a source for transferring charges from/to a floating gate of the memory transistor Q7. The transfer gate transistor Q8 has a gate receiving a clock signal CLK for providing timing for transferring data from the static RAM cell portion 1 to the EEPROM cell portion 2 or vice versa. The memory transistor Q7 has a control gate receiving a signal PRO for providing timing for writing and erasing information of the memory transistor Q7. The transistor Q9, which has a diode-connection, has one conduction terminal connected to a drain of the memory transistor Q7 and other conduction terminal connected to a signal CLR for applying a potential to the drain of the memory transistor Q7 at the time of writing and erasing of data. Description is now made on operation.
A memory cell is selected by the word line WL. More specifically, when the potential on the selected word line WL attains an "H" level, the transfer gates Q5 and Q6 are turned on. As a result, outputs of the flip-flop, that is, the drains of the transistors Q1 and Q2 are connected to the bit lines BL and BL, respectively, so that information is read or written through the bit lines BL and BL.
Information is stored in a nonvolatile manner in the EEPROM cell portion 2, that is, in the memory transistor Q7 through the transfer gate Q8. Operation of writing, erasing and reading data in the memory transistor Q7 are the same as that in the memory transistor in the conventional EEPROM. More specifically, data written into the static RAM cell portion 1 is stored in a nonvolatile manner by causing the signals CLK, PRO and CLR and the power-supply potential V.sub.DD and the memory cell to be a suitable voltage at suitable timing. Operation of transferring information is described in the above described document of the prior art.
As described in the foregoing, since the conventional nonvolatile RAM memory cell is formed by a combination of the static RAM memory cell and the EEPROM memory cell, the number of transistors required for each memory cell is large, so that the area occupied by a memory cell is increased, which presents a large problem in improving integration. In addition, the number of signal lines is large, so that the structure and control operation of a circuit are complicated.